Hi,
Can someone please explain about Expanded Time Events Mode in Questasim,When it is used and when it is it advisable to use this feature.Does it impact our simulation results or decision making?
In reply to rajan passionate:
This is a public methodology forum not for too specific usage, however, I can explain this topic in general terms.
Debugging tools generally save the state of a signal at the end of the time slot whenever there is a change in the state of a signal. In RTL, and especially gete-level simulations, there can be many changes in a signal before it settles to a final state. Tools typically do not record all these changes as it becomes a performance penalty as well as taking up a lot of extra disk space.
But sometimes there glitches in your design and you need to see all the intermediate states (a glitch on a gated clock). Or sometimes there is a race condition between two signals and you need to know the exact order between changes. Then you need to turn on these options.
In reply to rajan passionate:
You might be interested in this: Verification Course Blog | VeriLog Courses | CVC
Regards
Srini
www.verifworks.com