In reply to samir singh:
Here is slightly more than a bit of explanation:
A forever is a procedural looping statement, equivalent to a while (1) loop. You can enter a forever loop at any time in the procedural flow of your code. You can use the break statement along with a number of other constructs to get out a forever loop.
An always block is a declarative construct. It declares a procedural block of code as an independent process starting at time 0. When the procedural block of code finishes, the block repeats endlessly. There is no way to terminate the process started by an always block other than ending the simulation. An always block may only appear in the declarative section of a module or interface. You cannot put an always block inside a procedural block of code.
I was not entirely correct in my original answer about the if statement because there are many different kinds of if constructs in SystemVerilog. Your code fragment does not give enough context to determine which kind is being used.
There is the if construct that is a procedural conditional branching statement. You can put that if within any procedural block, and each branch is another procedural block. So you cannot put an always block inside a procedural branch of an if statement. I’m assuming this is the kind of if construct you intended.
There is also a declarative if-generate construct. This if-generate construct gets evaluated during compilation/elaboration, not at run time. Each branch of the if-generate can be another declarative block, which may contain an always block. See section 27.5 Conditional generate constructs in the LRM for more details.