Use internal signals as control signal in UVM, uvm_hdl_read()

UVM
1

I want to use internal signals as control signal, done_o and start_i signal.
But when i use uvm_hdl_read(path, value), the value from the function is always 0. I don’t know why, and from the waveform, its value is not 0 somtimes.

please tell me how to solve this problem. Maybe use wait_for_data();

this is my code

bit done_o;
while(1)begin
uvm_hdl_read(path, done_o);
if(done_o == 1'd1)begin
/////do some operations.
end
end
2

In reply to jundijiujieke:

You may need to use simulator specific options to enable uvm_hdl_read() functionality. Refer to your tool’s documentation or contact your vendor support team for additional assistance.

It is highly recommended to not access any signal values outside of your agent’s BFM interface. You should approach your verification methodology in the same way that a software developer would. How do you determine when ‘done_o’ is asserted? Do you read a register? Wait for a minimum time (i.e. clock cycles)? You shouldn’t read any DUT signals or values that aren’t available from your top level interfaces.

3

In reply to cgales:

This done_o signal is internal signal(not the top siganls), I want read its value, and change my sequence according its value. Why i can’t use internal signals

4

In reply to jundijiujieke:

If it is required to wait for the done_o signal, how would an end user know that this signal changes?

Sequences are required to be transactional based. The behavior of a sequence can change based upon the return values in previous transactions. You should never use signal values directly to change sequence behavior.

If you really want to get values of internal signals, then you should create another agent which monitors these signals and returns their values as a sequence_item.

5

In reply to cgales:

Im actually facing this issue a lot…
in Analog Mixed signal the DUT models may have variables that enabled model features that will never be accessed by a software developer. but they DO need to be used to verify the system.
(enable noise generation in block A, set model simulation temperature in block C, so that software routines to compensate for temperature changes can be validated to work correctly,

my solution will be to use the systemverilog BIND function to bind an interface to the variable being observed or manipulated.

I note that this interface may need to be accessed by sequences… or it might need an agent.

The reason I came to the forum was to decide how to register the interface.