Use #delay in uvm_components

UVM
,
1

Hello Verification Academy!
Please help me understand why

`include "uvm_macros.svh"
`include "port_export.sv"

package env_pkg;
  import uvm_pkg::*;
  import pe_pkg::*;
  
  // Pusher
  class pusher extends uvm_component;
    
    uvm_blocking_put_port #(trans1_t) put_port;
    trans1_t trans;
    
    function new (string name, uvm_component parent = null);
      super.new(name, parent);
      put_port = new("put_port", this);
      trans = new;
    endfunction
    
  task run_phase(	uvm_phase 	phase	);
      task run();
      trans.i = 5;
      put_port.put(trans);
      //#10;
      trans.i = 50;
      put_port.put(trans);
      //#10;
      trans.i = 500;
      put_port.put(trans);
      //#10;
      trans.i = 5000;
      put_port.put(trans);
    endtask
  endclass: pusher
  

  // Environment
  class env extends uvm_env;
    //`uvm_component_utils(env)
    
    pusher psh;
    port_export pe;
    
    function new (string name = "env");
      super.new(name);
      psh = new("pusher", this);
      pe = new("port_export", this);
    endfunction
    
    function void connect_phase(uvm_phase phase);
      psh.put_port.connect(pe.exp_port);
    endfunction
    
    
    function void start_of_simulation_phase(uvm_phase phase);
      uvm_top.set_report_verbosity_level_hier(UVM_HIGH);
      uvm_top.set_report_severity_action_hier("prd", UVM_DISPLAY);
    endfunction: start_of_simulation_phase
    
    task run_phase(	uvm_phase 	phase	);
    //task run();
      #1000 ;
	  global_stop_request();
    endtask
    
  endclass: env
endpackage: env_pkg

module test;
  import uvm_pkg::*;
  import pe_pkg::*;
  import env_pkg::*;

  env e;
  
  initial begin
    e = new("env");
    run_test();
  end
  
endmodule


//-------------------------------------------------
`include "uvm_macros.svh"

package pe_pkg;
  import uvm_pkg::*;

  //////////////////////////////////////////////////////
  // Types of transactions
  class trans1_t extends uvm_transaction;
    int i;
  endclass: trans1_t
  
  class trans2_t extends uvm_transaction;
    int k;
  endclass: trans2_t
  
  
  //////////////////////////////////////////////////////
  // Producer
  class producer extends uvm_component;
    
    uvm_blocking_put_imp #(trans1_t, producer) imp_port;
    trans2_t pro_trans;
    
    function new (string name, uvm_component parent = null);
      super.new(name, parent);
      imp_port = new("imp_port", this);
      pro_trans = new;
    endfunction
    
    task put(trans1_t t);
      pro_trans.k = t.i + 1;
      `uvm_info("prd", $psprintf("PRD received i = %d, sent k = %d", t.i, pro_trans.k), UVM_HIGH);
    endtask
	
  endclass: producer
  

  //////////////////////////////////////////////////////
  // Connect 2 modules
  class port_export extends uvm_component;
    uvm_blocking_put_export #(trans1_t) exp_port;
    
    producer p;
    
    function new (string name, uvm_component parent = null);
      super.new(name, parent);
      p = new("producer", this);
      exp_port = new("exp_port", this);
    endfunction
    
    
    function void connect();
      exp_port.connect(p.imp_port);
    endfunction
  endclass: port_export
endpackage: pe_pkg
2

A few problems with your testbench.

If you use stop_request() and/or global_stop_request(), then you will need to use the plusarg +UVM_USE_OVM_RUN_SEMANTIC, otherwise your testbench will end prematurely without awaiting your stop_request().

The UVM way to end a test is to use objections.

task run_phase(	uvm_phase 	phase	);
    //task run();
    phase.raise_objection(this); 
      #1000 ;
    phase.drop_objection(this);
endtask

Another problem is that you are putting the same transaction over and over again without cloning it. You are modifying the same i variable.

3

Thanks for the help!!

Еverything works as I wanted.