Use cases of different types of ports


A quick clarification in uvm ports, ie:

Till now in most of my test benches I always use tlm analysis ports. But I am wondering whats the difference between the following ports.

Whats the use case for each of them.

b) Lets assume I want to connect two components across the hierarchy. also lets say the source is subcompA and target is subcompB, and subcompA is instanced in compA and subcompB is instanced in compB. So how should I connect the ports here, is it option 1) or 2) or something else.

  1. Port(in subcompA) → port (in compA) → export (in compB) → impl Port (in subcompB)
  2. Port(in subcompA) → export (in compA) → export (in compB) → impl Port (in subcompB)

Thanks for the help

In reply to nipradee:

The earliest forms of the UVM (AVM) borrowed heavily from SystemC TLM which contains many different protocols for untimed communication. But in practice over the years, only two communication channels from TLM get used: analysis port/exports, and Sequencer port/exports.

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In reply to dave_59:

Hi Dave Thanks for the pointers, very helpful.
Additionally for the sequencer ports/exports that you mentioned, could you please explain an example scenario on where thats actually getting used? Is it for the internal handshaking between the driver and the sequencer (I mean the part which uvm actually takes care of automatically, for the user) ?

Thanks for the help.

In reply to nipradee:

You see this only on the driver side with the uvm_seq_item_pull_port, and the corresponding sequence⟺driver API. The other side is internal to the uvm_sequencer.

It’s unfortunate that they made this so complicated by inventing a special communication channel just for sequences instead of adopting an existing TLM put/get.