We have USB host BFM to verify USB 2.0 fullspeed device DUT. BFM is in verilog.
Now we want to verify USB device DUT in UVM. We are thinking to use same verilog host BFM in our UVM environment by creating a SV wrapper around BFM, so that we can use existing BFM tasks.
I would like to know what is best way for this or suggestions for the same.
One approach is to convert your Verilog BFM to a SystemVerilog interface. This should be fairly straight forward, and then you can use this interface as part of your UVC. The driver can then call the appropriate functions/tasks in the interface as required.
In reply to cgales:
The verilog BFM is in form of different modules each having different tasks like ctrl_rd, ctrl_wr, in_trans, out_trans. Each of those tasks in turn call different tasks for different purposes.
Is your method still useful or we should instantiate bfm along with DUT and call bfm tasks directly from usb agent driver.
In reply to Chandrashekhar Goudar:
Without seeing your code and understanding how it is organized, it’s hard to give specific recommendations. You can’t call BFM tasks directly from your driver because you aren’t allowed to make hierarchical references from your class based testbench. You will need to create an intermediate interface which you can then use to call BFM tasks/functions. It is usually easier to put your BFM code into your interface and limit the need to relay calls through the interface.