Usage of 'slv_if.slv_cb_drv' inconsistent with 'clocking block' object

UVM
,
1

sir, I’m getting an error as “Usage of ‘slv_if.slv_cb_drv’ inconsistent with ‘clocking block’ object”,
what can I rectify it?
This is the interface file


interface router_if(input bit clock);
  logic resetn;
  logic read_enb;
  logic pkt_valid;
  logic [7:0]data_in;
  logic [7:0]data_out;
  logic valid_out;
  logic error,busy;

  clocking slv_cb_drv@(posedge clock);
    default input #1 output #1;
    output read_enb;
    input valid_out;
  endclocking

  clocking slv_cb_mon@(posedge clock);
    default input #1 output #1;
    input data_out,read_enb,valid_out;
  endclocking

  clocking mstr_cb_drv@(posedge clock);
    default input #1 output #1;
    output data_in,pkt_valid,resetn;
    input error,busy;
  endclocking

  clocking mstr_cb_mon@(posedge clock);
    default input #1 output #1;
    input resetn,data_in,pkt_valid,error,busy;
  endclocking

  modport MSTR_DRV(clocking mstr_cb_drv);
  modport MSTR_MON(clocking mstr_cb_mon);
  modport SLV_DRV(clocking slv_cb_drv);
  modport SLV_MON(clocking slv_cb_mon);
endinterface

In this below task from slave monitor I’m getting error in line 47 and also in all lines like 49,51,54, etc where I’ve DECLARED clk delay using interface clocking delay


task router_slave_driver::send_to_dut(read_xtn xtn);
  `uvm_info("Router_slv_driver",$sformatf("printing from driver\n%s",xtn.sprint()),UVM_LOW)

  @(slv_if.slv_cb_drv);//line 47
  while(!slv_if.slv_cb_drv.valid_out)
    @(slv_if.slv_cb_drv);//49
  repeat(xtn.no_of_cycles)
    @(slv_if.slv_cb_drv);//51
  slv_if.slv_cb_drv.read_enb<=1'b1;
  wait(!slv_if.slv_cb_drv.valid_out);
  while(slv_if.slv_cb_drv)//54
    @(slv_if.slv_cb_drv);
  slv_if.slv_cb_drv.read_enb<=1'b0;
  //slv_agt_cfg.drv_data_count++;
  @(slv_if.slv_cb_drv);
endtask

Thanks
durga prasad

2

In reply to Maddala Durga Prasad:

Your question states that the code is from slave monitor, but the code provided states ‘router_slave_driver’. Are you providing the correct code?

What is ‘slv_if’ declared as?

3

In reply to cgales:

First of all, thanks for your reply, sir.
sorry sir, the error is from slave driver not from slave monitor, my mistake,
//The interface file is correct which I’ve declared at the beginning.
//This is the slave monitor code, please look into it, line number 47,49,52, etc. are errors


class router_slave_driver extends uvm_driver #(read_xtn);

  `uvm_component_utils(router_slave_driver)

  virtual router_if.SLV_DRV slv_if;

  router_slave_agent_config slv_agt_cfg;

  extern function new(string name="router_slave_driver",uvm_component parent);
  extern function void build_phase(uvm_phase phase);
  extern function void connect_phase(uvm_phase phase);
  extern task run_phase(uvm_phase phase);
  extern task send_to_dut(read_xtn xtn);
  extern function void report_phase(uvm_phase phase);
endclass

function router_slave_driver::new(string name="router_slave_driver",uvm_component parent);
  super.new(name,parent);
endfunction

function void router_slave_driver::build_phase(uvm_phase phase);
  if(!uvm_config_db #(router_slave_agent_config)::get(this,"","router_slave_agent_config",slv_agt_cfg))
    `uvm_fatal("router_slave_driver","unable to get the slv_agt_top,have you set it?")
  super.build_phase(phase);
endfunction

function void router_slave_driver::connect_phase(uvm_phase phase);
  slv_if=slv_agt_cfg.slv_if;
  super.connect_phase(phase);
endfunction

task router_slave_driver::run_phase(uvm_phase phase);
  forever begin
    req=read_xtn::type_id::create("req");
    seq_item_port.get_next_item(req);
    send_to_dut(req);
    seq_item_port.item_done();
  end
endtask

task router_slave_driver::send_to_dut(read_xtn xtn);
  xtn=read_xtn::type_id::create("xtn");
    @(slv_if.slv_cb_drv);//line 47
  while(slv_if.slv_cb_drv.valid_out!==1'b0)
    @(slv_if.slv_cb_drv);//49
  repeat(xtn.no_of_cycles)
    begin
      @(slv_if.slv_cb_drv);//52
    end
  slv_if.slv_cb_drv.read_enb<=1'b1;
  wait(!slv_if.slv_cb_drv.valid_out)
  while(slv_if.slv_cb_drv)
  @(slv_if.slv_cb_drv);
  slv_if.slv_cb_drv.read_enb<=1'b0;
  //slv_agt_cfg.drv_data_count++;
  @(slv_if.slv_cb_drv);
  `uvm_info("Router_slv_driver",$sformatf("printing from driver\n%s",xtn.sprint()),UVM_LOW)
endtask

function void router_slave_driver::report_phase(uvm_phase phase);
  //`uvm_info(get_type_name(),$sformatf("Report:router read driver sent %0d transactions",slv_agt_cfg.drv_data_count),UVM_LOW)
  super.report_phase(phase);
endfunction

//this is slave agt config code
class router_slave_agent_config extends uvm_object;

  `uvm_object_utils(router_slave_agent_config)

  virtual router_if slv_if;

  uvm_active_passive_enum is_active=UVM_ACTIVE;

  extern function new(string name="router_slave_agent_config");
endclass

function router_slave_agent_config::new(string name="router_slave_agent_config");
  super.new(name);
endfunction

Is this information enough for you sir to debug this?

thanks you sir,
durga prasad.

4

In reply to Maddala Durga Prasad:

Remove all modport definitions in your interface. They are design constructs and should not be used for verification.

In your driver, you want:


virtual router_if slv_if;

There are a few other issues in your code you should fix, but this should get you running.

5

In reply to cgales:

But how can I give direction to signals for master and slave drivers and monitors without modports?