Usage of "pullup" and "bufif0" Switch-level modelling constructs in Verilog

SystemVerilog
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1

I am experimenting with how the “pullup” and “bufif0” switch-level constructs work in Verilog. The concept is to be used in an UVM-based I2C top module for generating the “sda” and “scl” signals.

I have implemented a stand-alone experimental code in Verilog to observe the signal value changes through the use of “pullup” and “bufif0” constructs, as follows:

module top();

  wire x, y;
  wire f, g;
  supply0 gnd;

  bufif0(x, gnd, f);
  bufif0(y, gnd, g);

  pullup(x);
  pullup(y);

  initial #10 $stop();

endmodule

My expectation is that the “x” and “y” signals should be pulled up to 1’b1 and the value propagated to “f” and “g” respectively through the tri-state buffer construct (bufif0). However, what I get is as follows:
“x” - remains at X (value: 65X)
“y” - remains at X (value: 65X)
“f” - Z (high impedance)
“g” - Z (high-impedance)

Am I missing something in the code? Can someone help me resolve the issue or point me to references for the same?

Regards

2

In reply to kautilya87:
The bufif0 primitive is unidirectional. You need to use the tranif0 to get bidirectional signal flow. See section 28.8 Bidirectional pass switches in the LRM.