Usage of parameter inside a function

SystemVerilog
,
1

Hi,
I’m trying to use a parameter in a function. This function is present inside a module and the module is a parameterised module: Example:

module usb #(packet_length, speed) ();

generate
if (speed == full_speed) begin : full_speed
function [63:0] read_data;
input [3:0] id;
case [id]:
4’b000 : read_data = top.abc.xyz.data;

endcase
endfunction
end else begin : high_speed
function [511:0] read_data;
input [3:0] id;
case [id]:
4’b000 : read_data = top.def.ghi.data;

endcase
endfunction
end
endgenerate

  1. The compilation gives error saying it cannot find the path of read_data
  2. The path used when in full_speed does NOT exist when the test is compiled with high_speed and vice-versa.
  3. How can I use the parameter that is passed to this module to generate the functions appropriately?

Any help is appreciated.

Thanks

2

What you have done is declared the functions full_speed.read_data() or high_speed.read_data(), not just the simple read_data().

What you can so is

module usb #(packet_length, speed) ();
  wire [511:0] local_data;
  if (speed == full_speed) // if-generate
    assign local_data = top.abc.xyz.data;
  else
    assign local_data = top.def.ghi.data;

  function [63:0] read_data(input [3:0] id);
    case [id]:
    4'b000 : read_data = local_data;

    endcase
  endfunction
endmodule

You could also do

module usb #(packet_length, speed) ();
  function [63:0] read_data(input [3:0] id);
    case [id]:
    4'b000 : read_data = (speed == full_speed) ? top.abc.xyz.data : top.def.ghi.data;

    endcase
  endfunction
endmodule

I’m guessing your code is much more complex than what you have shown, so you will need to show all your requirements to be able to help you further.

3

In reply to dave_59:

Hi Dave,
Thanks for your response. Both the solutions that you have suggested does not work. The point to be noted here is that the hierarchical reference top.abc.xyz does NOT exist (ie, abc module does not get instantiated when speed is high speed. SImilarly, def module does NOT get instantiated in the design when speed is full speed. So, when the above assignments are used, the compilation gives out error saying its not able to find one of the paths (depending on the mode in which the test is run).

The speed is being passed into the module as a parameter. How can a parameter variable be used as a define? Can a parameter be used as a define at all?
like: ifdef speed (will the compiler enter tthis section when speed is 1) and go to the else part when speed is 0?

The main problem here is that only one hierarchy exists at any point of time and the other does NOT exist. So, how do we tell the compiler not to compile the part of code whose hierarchy does not exist .

Thanks

4

In reply to Ramyas:

This code I showed works if the instantiations are controlled be a similar generate statement. You will need to show us more of your code. You can’t use parameters to control ifdef as ifdef’ are pre-processed before any parameters are known.

package p;
   typedef enum {FULL_SPEED, HIGH_SPEED} speed_e;
endpackage

module top import p::*;#(speed_e speed = HIGH_SPEED)();
   if (speed == FULL_SPEED) begin : abc
     abc xyz();
      end : abc
   else begin : def
     def ghi();
   end : def
   
   usb #(speed) u();

endmodule : top

module abc;
   bit [511:0] data = 'h555555555;
endmodule : abc
module def;
   bit [511:0] data = 'h555555555;
endmodule : def

module usb import p::*; #(speed_e speed)();

   wire [511:0] local_data;
   if (speed == FULL_SPEED) // if-generate
     assign local_data = top.abc.xyz.data;
   else
     assign local_data = top.def.ghi.data;

   initial $displayh(local_data);
endmodule : usb