System verilog support continuous range inside a ‘dist’. For example
y dist {
[1:1000] :/ 40,
1500 :/ 60
}
Does it support multiple random elements. For example
{1,3,2,6} :/ 40
Is it possible to use ‘inside’ in ‘dist’ ?
Yes to your questions
import uvm_pkg::*;
`include "uvm_macros.svh"
class randobj;
rand integer a,b, c;
rand bit reset;
// reset ==1'b1 1% of the time
// reset ==1'b0 99% of the time
constraint c_reset {reset dist {1'b1:=1, 1'b0:=99}; }
// a==1 @weight=1; a==2 @weight=3, a==4 to 5 @weight=5,
// a==value(b to b+2) EACH @weight=number of entries in this range /3
// total weight= 1+3+5+5+1+1+1 = 17;
// ADDED a inside values
// Prob (a==1) is 1/17; prob(a==4) is 5/17
constraint cst_c1 { a dist {1:=1, 2:=3, [1:500]:=5, [b:b+2]:/3};
a inside {[2:410], 450, [475:480]}; }
endclass
module ct;
randobj obj=new();
initial repeat(25) begin
if (!randomize(obj)) $display("error");
`uvm_info("obj", $sformatf("obj.a=%d, obj.b=%d, obj.reset=%b",
obj.a, obj.b, obj.reset), UVM_MEDIUM);
end
endmodule
simulation results
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 323, obj.b=-1962160428, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 373, obj.b= 1610605922, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 19, obj.b= -570888616, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 327, obj.b=-1237320078, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 124, obj.b= 1510582120, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 96, obj.b= 1361594760, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 288, obj.b= 1153239299, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 299, obj.b= 1763043026, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 59, obj.b= 1609910517, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 252, obj.b= -343651442, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 243, obj.b= 1183482975, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 243, obj.b=-1782132643, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 135, obj.b=-1142362001, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 336, obj.b=-1709624191, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 193, obj.b= 1445644885, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 258, obj.b= 117269902, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 124, obj.b=-1344482007, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 270, obj.b= 1483916278, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 168, obj.b= -815500200, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 185, obj.b=-1832948933, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 216, obj.b= -654692261, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 400, obj.b= 1535384952, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 44, obj.b= 6940479, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 192, obj.b= 439189657, obj.reset=0
# UVM_INFO ct.sv(23) @ 0: reporter [obj] obj.a= 299, obj.b= 1174315181, obj.reset=0
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115