Usage of Bit bash sequence

UVM
,
1

I am using UVM inbuilt sequence for register bit bash testing and we don’t want to check one of the register in our model for bit bash testing. For this scenario we have done following configurations:

uvm_resource_db#(bit)::set({“REG::”,regs.DEV_CONT_STATUS_REG_S_h.get_full_name(),“.*”},“NO_REG_BIT_BASH_TEST”, 1, m_sequencer);
regs.reset();

regs is handle of our register block,
DEV_CONT_STATUS_REG_S_h is our register for which we want to disable the bit bash testing.

But it seems that this is not working and we can see that this register is being used in bit bash testing.
Is this configuration correct?
Please suggest if it is wrong.

Also, we are doing it in body of our sequence.

Thanks in advance

2

In reply to shreemant.vats:

Hi Shreemant,
could you please try to set the “NO_REG_BIT_BASH_TEST” from your test in build phase.

function void build_phase(uvm_phase phase);
uvm_resource_db#(bit)::set({“REG::”,regs.DEV_CONT_STATUS_REG_S_h.get_full_name()},“NO_REG_HW_RESET_TEST”, 1, this);
super.build_phase(phase);
endfunction

-Abhijeet