Up-downsizer

SystemVerilog
1

I am learning up-down sizer in AXI interconnect, please explain with example of equations on page 14 of below link…specially

si.conv_ratio = (2**si.SIZE) / cb.Bytes

cb.conv_ratio = (2**cb.SIZE) / mi.Bytes

si.downsize_LEN = (si.LEN+1) * si.conv_ratio - 1

cb.downsize_LEN = (cb.LEN+1) * cb.conv_ratio - 1

2

I am learning up-down sizer in AXI interconnect, please explain with example of equations on page 14 of below link…specially
si.conv_ratio = (2si.SIZE) / cb.Bytes
cb.conv_ratio = (2cb.SIZE) / mi.Bytes
si.downsize_LEN = (si.LEN+1) * si.conv_ratio - 1
cb.downsize_LEN = (cb.LEN+1) * cb.conv_ratio - 1

link : AMD Adaptive Computing Documentation Portal