Unique String Registration in Factory

UVM
,
1

I have following code ( slightly modified ) from Rich Edelman’s paper “Does the Factory say Override”


  `include "uvm_pkg.sv"
  `include "uvm_macros.svh" 
  
   import  uvm_pkg::*;

  class  base #( SIZE = 128 )  extends  uvm_component ;

     localparam  type_name  =  $sformatf("base#(%0d_%0s)" , SIZE , ( ( ( SIZE <<  24 ) > 0 )  ?  "unsigned"  :  "signed" )  ) ;  //  [A]

     typedef  uvm_component_registry #(  base #( SIZE ) , type_name )  type_base ;

     function  string  get_type_name() ;
         return  type_name ;
     endfunction    
 
      function new ( string name , uvm_component parent ) ;
       super.new(name,parent);
      endfunction

  endclass

module  String_Specialization_via_Sign ;
  
  base #( 128 ) b1 ;

  parameter  int  unsigned  UINT32  =  128 ;

  base #( UINT32 )  b2 ;


  initial  begin

   $display(" b1 :: type_name  is %0s " , base #( 128 ) :: type_name );

   $display(" b2 :: type_name  is %0s " , base #( UNINT32 ) :: type_name );
   
  end


endmodule

I have a few questions ::

[Q1] Is [A] valid based on LRM ? Some Simulators throw Compilation Error .
I even observe that for the same simulator , it works with previous version but throws error with newer version

[Q2] Via Specializations b1 and b2 there exists Two Separate Registration in Type based factory .

  So  shouldn't  there  exist  separate  Registration  in  String  based  Factory  as  well  ?


              //  As  per  the  Original  Code  in   Paper  ::
      Eg  ::   localparam  type_name  =  $sformatf("base#(%0d)" , SIZE ) ;  //  Same  String  Registration for  b1  and  b2  !!

[Q3] The logic I have used above is hardcoded for Value as 128 .

Is there a generic logic through which I could know whether the value parameter is Signed OR Unsigned ?

  Is  there  a  System  Function  for  the  Same  in  Verilog  /  SystemVerilog  ?
2

In reply to ABD_91:

  1. The validity of [A] is at best ambiguous in the current LRM, but is now explicitly valid in the next revision on the IEEE 1800 LRM.
  2. Yes, there will now be two unique string factory registrations for the two class types.
  3. See Determining whether type parameter is Signed or Unsigned ? | Verification Academy
3

Hi Dave ,

A few more questions to conclude the thread .

[A] For 3 , the following logic doesn’t work :: Size_Casting

The Output is not as per intention .

I expect “signed” for Signed parameter Specialization whereas I Observe “unsigned” .

SV LRM 6.24.1 ::

" The signedness shall pass through unchanged i.e the signedness of the result shall be the self - determined signedness of the expression inside the case "

As '1 is unsigned , I believe that’s why we Observe “unsigned” in O/P !!

[Q1] Is there any alternative logic ?

[B] I tried a Code based on Shift logic :: Shift_Logic

 Here  too  the  output  isn't  as  per  expectation . 


 Result  of   ( bs_3_0  <<  1 )  and  ( ls_9_0  <<  5 )  is  ::

     -2  and   -384   however   result  of 

 ( ( bs_3_0  <<  1 ) > 0 ) and ( ( ls_9_0  <<  5 ) > 0  ) is  1,  why ??

LRM 11.4.10 says :: "The signedness is determined by the left-hand operand "

[Q2] As all operands are signed , why do I still Observe 1 ??

[C] State of the Value parameter .

 Within  a  Value  parameterized  class  how  can  I  know

 whether  the  actual  to  the  Value  parameter  is  2 - state /  4 - state  ?



 class  base #( SIZE = 128 )  ;

   //  localparam  string  STATE  =  Need  logic  here  !! 
   
   //   STATE  should  be  either  "4_state"  OR  "2_state"  !!
  
 endclass

  parameter  bit  signed [ 3 : 0 ] bs_3_0 =  7 ; 

 parameter  logic  signed [ 9 : 0 ] ls_9_0 = 20 ;

 base #(  bs_3_0 )  b1  ;  //  base #( bs_3_0 ) :: STATE  should  be  "2_state"

 base #( ls_9_0 ) b2 ;    //  base #( ls_9_0 ) :: STATE  should  be  "4_state"

[Q3] Any suggestions for the logic ?

  I  tried  using  ::  


     localparam  T1   =   SIZE'( 'X )  ;  

     localparam  STATE  =  $sformatf("%0s" ,
       
                               (  (  T1 === 'X  )  ?  "4_state"  :  "2_state"  )  ) ;

But this gives “4_state” ALWAYS !!

Thanks in advance .