Unique array elements without rand or randc

SystemVerilog
,
1

I have a variable logic [31:0] id which is not declared as rand or randc. I need different id’s each time into an array logic [31:0] id_array [16].

logic [31:0] id;
logic [31:0] id_array [16];
foreach(id_array[i]) begin
std::randomize(id);
id_array[i] = id;
end

In the above code, there is a possibility of getting duplicate ids in the array. How do I change the code to get unique ids in the array ?

2

In reply to AMARDEEP R PALURU:

I would change this to

logic [31:0] id;
logic [31:0] id_array [$];
repeat (16) begin
  std::randomize(id) with {!(id inside {id_array});};
  id_array.push_back(id);;
end
3

In reply to AMARDEEP R PALURU:

If your tool supports 1800-2102 you can also do

logic [31:0] id_array [16];

  std::randomize(id_array) with {unique {id_array};};