Unique and priority case

SystemVerilog
,
1 
module casee; 

initial 
begin 

for(int a = 0;a<4;a++) 
priority casez(a) // values 4,5,6,7 cause a warning 
3'b00?: $display("0 or 1"); 
3'b0??: $display("2 or 3"); 
endcase 

end 
endmodule

RESULTS:

0 or 1
0 or 1
2 or 3
2 or 3
I couldn’t understand this.can anyone explain ?

2

In reply to suresh M:

Hi Suresh,

Here casez_option 3’b00? can match value of either 3’b000 or 3’b001.
While casez_option 3’b0?? can match values 3’b000,3’b001,3’b010,3’b011.

While priority keyword gives priority to first match.

i.e values 'b000 and 'b001 can be matched from either 3’b00? or 3’b0?? but because of priority first matched case_statement gets executed.

Values 4,5,6,7 are not getting satisfied with any of the provided casez_options so warning is generated !!

3

In reply to Digvijaysinh Suryavanshi:
The
unique and
priority keywords don’t change the execution the
case statement. But they do give design intent to synthesis tools so that they can optimize their implementation, and simulation tools are required to give warnings if the simulation does not match the intent. See the LRM or this paper for more details.

4

In reply to dave_59:

Thank you for clarification and providing reference link.