I am recently learning system verilog in a sample code using struct data type I was getting some errors
like :
** Error: (vlog-13069) C:/intelFPGA/17.1/sloving.sv(6): near “=”: syntax error, unexpected ‘=’.
** Error: C:/intelFPGA/17.1/sloving.sv(6): (vlog-13205) Syntax error found in the scope following ‘stud1’. Is there a missing ‘::’?
module datatypes();
typedef struct{integer slno;string name;int unsigned reg_no;real ssc; real biep;real be;longint unsigned ph_no;} value;
value stud1;
value stud2;
value stud3,stud4,stud5,stud6,stud7;
stud1 = '{1,“jaith”,34,9.0,8.6,7.3,9052422xxxx};
stud2 = '{2,“supriya”,88,9.8,9.6,7.6,90Xxxxxxx};
stud3 = '{3,“jayasri”,27,9.0,10,8.5,9052422xxxx};
stud4 = '{4,“bhargav”,40,9.0,9.8,7.5,9052422xxxx};
stud5 = '{5,“gowri”,22,9.0,8.6,7.3,9052422xxxx};
stud6 = '{6,“naveen”,17,9.0,8.6,7.3,9052422xxxx};
stud7 = '{7,“divya”,34,9.0,8.6,7.3,9052422xxxx};
$display(“%p/n %p/n %p/n %p/n %p/n %p/n %p/n”,stud1,stud2,stud3,stud4,stud5,stud6,stud7);
endmodule
In reply to jayath2000:
You are using procedural assignments in a non-procedural block of code. You can declare and initialize your variables at the same time, or you can enclose the assignments/$display within an initial block.
Also, you have invalid digits in the ph_no field as ‘x’ isn’t appropriate for a longint unsigned.