Unexpected results for Dynamic delay range

SystemVerilog
,
3

In reply to plin317:
It looks like I need to change the (vdiff>=0, to vdiff>0


sequence dynamic_delay(count);
        int v;
      (count<=0) or ((1, v=count) ##0 (v>0, v=v-1) [*0:$] ##1 v<=0);
    endsequence // dynamic_delay
  sequence dynamic_delay_lohi_sq(d1, d2, sq);
        int v1, vdiff;
          ( (1, v1=d1, vdiff=d2-d1) ##0 dynamic_delay(v1)   ##0     
              (vdiff>0, vdiff=vdiff - 1)[*1:$] ##0 sq); // changed from diff>=0 
    endsequence

Imade the change in
https://verificationacademy.com/forums/systemverilog/sva-package-dynamic-and-range-delays-and-repeats
Thanks,

Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.