Ben,
As we discussed at the top of this thread, sequence ‘dynamic_delay_lohi_sq’ has a limitation when sub-sequent sequence doesn’t match even after ##(dyn_max). The assertion fails at next clock rather than ##(dyn_max)'th clock.
Refer edalink +define+M4.
Instead of failure at T:55 the assertion fails at T:65 due to repeat sequence ending.
Your later suggested the following ::
sequence dynamic_delay_lohi_sq(d1, d2, sq);
int v1, vdiff;
dynamic_delay(d1)##0
(sq or
(1, vdiff=d2-d1) ##0 (vdiff>0, vdiff=vdiff - 1)[*1:$] ##1 sq);
endsequence
which works for all scenarios.
The same was updated in sva-package-for-dynamic-delays in Nov 2023 but that update has been lost ever since the forum upgrade.