Understanding intersect operator

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Hi Ben ,
Yes I do understand that the right sequence should be 1[*4:10] , but even when using 1[*10]
why is it that assertion fails at t:35 specifically ? i.e how is the consequent evaluated ?

(1) For the 1st stimulus , ‘sig’ is True throughout simulation :


     initial begin
      #04 ; sig = 1 ;
      #90 ; 
      #5 ; $finish();
    end

sig[*1] is True at t:5 , sig[*2] is True at t:15 , sig[*3] is True at t:25 , sig[*4] is True at t:35 .
My understanding is that the intersect operator fails as soon as either the left or right sequence is false , so at t:45 wouldn’t sig[*4] be considered false ?

(2) For the 2nd stimulus , ‘sig’ is False at t:45 :


     initial begin
      #04 ; sig = 1 ;
      #40 ; sig = 0 ; 
      #60 ;
      #5 ; $finish();
    end

As ‘sig’ is false at t:45 , I expected the assertion to fail at t:45 .
Yet I see the assertion fails at t:35