Dear All,
I’m trying to understand about copying handle of systemverilog and referring the below code.
class parent_class;
bit [31:0] addr;
function display();
$display("Addr = %0d",addr);
endfunction
endclass
class child_class extends parent_class;
bit [31:0] data;
function display();
super.display();
$display("Data = %0d",data);
endfunction
endclass
module inheritence;
initial begin
parent_class p=new();
child_class c=new();
c.addr = 10;
c.data = 20;
p = c; //assigning child class handle to parent class handle
c.display();
end
endmodule
and I can get the below values.
ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Loading snapshot worklib.inheritence:sv .................... Done
ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
ncsim> source /incisiv/15.20/tools/inca/files/ncsimrc
ncsim> run
Addr = 10
Data = 20
But I can’t understand how does c handle can have ‘Addr’ value?
and c class has only display function about data, but how does it display ‘Addr’?