Understandable testbench developed on SV UVM assertion based

SystemVerilog
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Can anyone pls suggest me good(Understandable) testbench developed on SV UVM assertion based.
For any IP.

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Can anyone pls suggest me good(Understandable) testbench developed on SV UVM assertion based. For any IP.

UVM and assertion-based verification are different concepts, though they can be integrated together. Specifically,

  1. UVM is a class-based framework to create a reusable verification environment.
  2. Concurrent assertion statements in SV specify properties that the DUT must adhere to, based on possible assumptions. SVA also can provide coverage on sequence of data events or on those properties.
  3. SV concurrent assertion statements are illegal in classes; thus, they cannot be written inside, nor can they be bound to class instances, such as UVM drivers or UVM monitors.
  4. The good news though is that assertions and UVM can work together by having assertions being hosted (or bound to) SV interfaces that are connected to UVM classes.
  5. I just wrote a paper for the next Verification Horizons Edition targeted for ARM TechCon 2013 (Oct, 29th – Oct, 31st). The theme of that issue is Verification Productivity. The title of that paper is Assertions Instead of FSMs/logic for Scoreboarding and Verification. Look for the paper at Questa Verification Environment for Simulation and Debug | Siemens Software
  6. In that paper, I address the fact that monitors, scoreboards, and verification logic are typically implemented using FSMs, logic, and tasks. With UVM, this logic is hosted in classes. The paper demonstrates another option of implementing some monitors and scoreboards using SVA assertions hosted in SV interfaces. The basic concept involves using assertion statements along with functions, called from sequence match items, to collect the desired scoreboard information, to compare expected results to collected data, and to trigger covergroups.
  7. My test vehicle for the simulatable demo is a UART transmitter. The advantage of having the assertion property record the received data in the interface is that the data is then available to a monitor in UVM, for example, to assemble it into a transaction object and broadcast it to the rest of the UVM environment via its analysis_port. This allows the data to be checked immediately in the assertion before the UVM monitor is even notified that the data is present. This simplifies the monitor code and ensures that only valid data transactions are communicated.

BTW, I explain SVA in my book SystemVerilog Assertions Handbook 3rd Edition (compliant to 1800-2012) along with many simulatable examples and with many guidelines.
Ben Cohen http://SystemVerilog.us

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In reply to ben@SystemVerilog.us:

thanks 4 sharing knowledge …