Unable to print array in chronological order

SystemVerilog
, ,
1

hi,
iam trying to print two arrays but it isnt coming in order. this is my pseudo code:


fork
begin
forever begin
@posedge(a_clk);
time1[n] =$time;
$fdisplay(fd, "time1[%d] is :%t",n,time1[n]); // fd is file handle 
end end

begin
forever begin
@posedge(a_clk);
time2[m] =$time;
$fdisplay(fd, "time2[%d] is :%t",m,time2[m]);
end end
join

output:
time1[0]=14562.125ns
time2[0]=14879.125ns
time1[1]=15789.125ns
time1[2]=15796.125
time2[1]=15876.125
time1[3]=15840.125ns
can you tell me how shall i print this in order?

2

In reply to Pooja.balachandran:

When you have two blocks executing in parallel, there is no determinate order of execution.

Where are variables m & n defined? There is nothing in your code which shows them changing? Where does this occur?

You should post a complete example that demonstrates your issue that others can run.

3

i had initialized n and m as global variables.


fork
begin
forever begin
@posedge(a_clk);
if(fmt[1:0]==2'h3|| type[1:0] ==2'h4)begin
time1[n] =$time;
$fdisplay(fd, "time1[%d] is :%t",n,time1[n]); // fd is file handle 
n++;
end end end
 
begin
forever begin
@posedge(a_clk);
if(hdr[7:0==8'h30||  hdr[7:0]==8'h40)begin
time2[m] =$time;
$fdisplay(fd, "time2[%d] is :%t",m,time2[m]);
m++;
end end end
join
4

In reply to Pooja.balachandran:

This is still not a complete example which demonstrates your issue. It’s difficult to ascertain what your environment is doing without seeing everything involved.

It’s possible that the parallel threads are caching their output, resulting in something that seems to be out of order. Have you tried $fflush after every $fdisplay call?

5

this is the logic that i am using in my uvm run phase . the rest are connect phase, build phase and declarations of interfaces and arrays.

no i haven’t tried $fflush after $fdisplay. whats the purpose of using that?