Hi,
Below is my Sequence :
class my_base_reg_seq extends uvm_reg_sequence;
`uvm_object_utils(my_base_reg_seq)
// Register the default p_seqeuncer
`uvm_declare_p_sequencer(my_vsequencer)
ral_block_MY_IP regmodel;
uvm_status_e status;
uvm_reg_data_t read_value;
uvm_reg regs[$];
function new(string name ="my_base_reg_seq");
super.new(name);
endfunction
task pre_body();
if(starting_phase !=null)
starting_phase.raise_objection(this,get_type_name());
assert(uvm_config_db#(ral_block_D_IP_SAFETY_BY_SW_SYN)::get(p_sequencer,"*","regmodel",regmodel)); // I am setting it from my env
regmodel.reset();
endtask
task post_body();
if(starting_phase != null)
starting_phase.drop_objection(this,get_type_name());
endtask
endclass : my_base_reg_seq
//==============================================================================//
// SEQUENCE: my_reg_rw_seq //
// Description: Running UVM bit bash sequence for every register //
//==============================================================================//
class my_reg_rw_seq extends my_base_reg_seq;
`uvm_object_utils(my_reg_rw_seq)
uvm_reg_bit_bash_seq reg_check_seq;
function new(string name="my_reg_rw_seq");
super.new(name);
endfunction
virtual task body();
reg_check_seq = uvm_reg_bit_bash_seq::type_id::create("reg_check_seq", null);
reg_check_seq.model= regmodel;
// Trying to exclude the below register
uvm_resource_db#(bit)::set({"REG::",regmodel.TEMP_FAULT.get_full_name(),".*"},"NO_REG_BIT_BASH_TEST", 1, this);
reg_check_seq.start(p_sequencer);
endtask
endclass
Below is my regmodel :
class ral_reg__TEMP_FAULT extends uvm_reg;
uvm_reg_field FLAG1;
uvm_reg_field FLAG2;
rand uvm_reg_field TM_FAULT;
uvm_reg_field RSVD;
function new(string name = "__TEMP_FAULT");
super.new(name, 32,build_coverage(UVM_NO_COVERAGE));
endfunction: new
virtual function void build();
this.FLAG1 = uvm_reg_field::type_id::create("FLAG1",,get_full_name());
this.FLAG1.configure(this, 1, 0, "RO", 0, 1'b0, 1, 0, 0);
this.FLAG2 = uvm_reg_field::type_id::create("FLAG2",,get_full_name());
this.FLAG2.configure(this, 1, 1, "RO", 0, 1'b0, 1, 0, 0);
this.TM_FAULT = uvm_reg_field::type_id::create("TM_FAULT",,get_full_name());
this.TM_FAULT.configure(this, 3, 2, "W1C", 0, 3'b000, 1, 0, 0);
this.RSVD = uvm_reg_field::type_id::create("RSVD",,get_full_name());
this.RSVD.configure(this, 27, 5, "RO", 0, 27'b000000000000000000000000000, 1, 0, 0);
endfunction: build
`uvm_object_utils(ral_reg_SbSWIP__TMC_0_FAULT)
endclass : ral_reg__TEMP_FAULT
class ral_block_MY_IP extends uvm_reg_block;
rand ral_reg__TEMP_FAULT TEMP_FAULT; // Declared in reg block
// Other parts including the build phase() are there.
endclass : ral_block_MY_IP
Now, When I run the test : I get below Error :
@@reg_check_seq.reg_single_bit_bash_seq [uvm_reg_bit_bash_seq] Writing a 1 in bit #0 of register “regmodel.TEMP_FAULT” with initial value 'h0000000000000000 yielded 'h0000000000000008 instead of 'h0000000000000000
I wanted to exclude this register from the bit bash testing, but why it is not getting excluded??
Can anyone please help me with it…???