Hello Dave,
I have one query related to “Local variable declarations inside an unnamed block”.
As per Verilog LRM,local variables can only be declared inside a named block only as shown below :
##############################
initial
begin:B1
integer i;
i = 5;
end
#############################
If we remove the name of the block,Xilinx throws a compilation error as “Declarations not allowed in unnamed block”.
But we have found that simulators like Riviera-pro,VCS,NCSIM supports the local declarations with-out naming the block . The below code could be executed in EDA playground with all the 3 simulators selected at least once without any compilation error .
##############################
initial
begin
integer i=5;
end
#############################
Could you please make it clear how this is allowed in the above 3 simulators ?
Thanks
Susmita