UART baud rate monitor

In reply to jayati3108:

The generation of baud_o depends on the divider latch register(DLR) value & the down counter. Once the value is loaded in DLR, the down counter gets loaded with DLR value & its keep decrementing every clock cycle, when the count becomes zero baud_o will be generated and again the counter will be reloaded back with the DLR value and process will continue.

You can write an assertion for checking the counter & baud_o generation based on above logic.