Two Clock in Clocking block

UVM
,
7

In reply to chr_sue:

Hi Chr_sue, Here’s my sample code

// my_Sequence
task body(); 
if (pkt_tx.rd_file == 1'b1) begin
 assert(pkt_tx.randomize());
end
 else begin
 #1009.700ns  $readmemh("./image_2_hex.txt", mem_array);
   if(vif.i_reset_n==1'b1) begin   
      for(int i=0;i<2000; i++) begin
      @(posedge vif.i_Pixel_clock);
      pkt_tx.i_pixel_data   <= mem_array[i];
  end
  
   start_item(pkt_tx);
     pkt_tx.signal1   <= 4'h4    ;
     pkt_tx.signal2   <= 4'h5    ; 
    // .
    // .
   finish item(pkt_tx);
 end 
 endtask

// Driver :
//Below drive_pixel and drive_framer task are mine 

  task drive_pixel(packet_trans  pkt_tx); 
      vif.drv_pxl_cb.i_pixel_data    <= pkt_tx.i_pixel_data  ;
      vif.drv_pxl_cb.signal1         <= pkt_tx.signal1  ;
          // .
          // .
      endtask
             
  task drive_framer(packet_trans   pkt_tx);        
      vif.drv_frmr_cb.signal2        <= pkt_tx.signal2;
         //  .
         //  .                
  endtask

//-------------Driver run_phase ------------//
  seq_item_port.get_next_item(pkt_tx);
     wait(vif.i_reset_n == 1'b1) 
      begin
          fork
             @(posedge vif.i_Pixel_clock)drive_pixel(pkt_tx);
             @(posedge vif.i_sys_clock)drive_framer(pkt_tx);
          join
      end
   seq_item_port.item_done();

For the clocking block in the interface, I have implemented as shown by Dave, with respect to two different clock