Two Clock in Clocking block

UVM
,
6

In reply to Yeptho:

interface my_itf(input clk1,clk2);

  wire signal;
  clocking cb1 @(posedge clk1);
    output signal;
  endclocking
  clocking cb2 @(posedge clk2);
    output signal;
  endclocking
  
endinterface

Assuming you have a virtual interface handle vif, you would drive the signal with either

  vif.cb1.signal <= something; 
  // or 
  vif.cb2.signal <= something;