In reply to ben@SystemVerilog.us:
Hi ben , The requirement has two parts. First part is whenever “a” comes ,at the same cycle b should come. Part two is I have applied an assertion for part a which is following
$rose(a) |-> $rose(b) ////a and b should rise at same time.
Next thing is what if “a” never came .Means a possibility of vacuous.For this there are two solutions .Solution one is apply an another assertion that checks that under certain conditions “a” should come but I dont want this thing. I want something that avoid this vacuous pass ,any other way round if possible .Otherwise I would have to write an another property to check rise of signal “a”.