In reply to prashantk:
…So I don;t want to allow this vacuous pass.
You need to clarify your requirements.
$rose(a) |-> $rose(b) state that a rose of a implies a rose of b
If you don’t want a vacuity in a property, use sequences as the property element, but that will mist likely NOT do what you want. For example, ap: assert property($rose(a) ##0 $rose(b)); means thta at EVERY cycle, you must have a $rose(a) forllowed by a $rose(b), an impossibility with a singly clocked assertion.
Write your requirements in English, and then write the assertion.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115