In reply to ben@SystemVerilog.us:
Hi Ben , I want my assertion that does not pass vacuously.Is there any way to do that.
For example :-
a sequence inside a property is like this …
$rose(a) |-> $rose(b)
But as you know the catch is if “a” doesn’t come then assertion passes vacuously. So I don;t want to allow this vacuous pass.Is there any to do that. Otherwise I have to write another property that checks the rose of “a”.