Turn off vacuous success in SystemVerilog assertions

In reply to pRoSpEr:

As for the question for me, I am not using pass action block. It is just that assertion success/failures/vacuous success are visible when visualizing the variable dump. In such a case a vacuous success may be a source of trouble for my team mates during verification.

If I understand you correctly, are you use variable dump from variables updated with the action blocks?
Have you tried the vpi_get?

… The static information about assertions can be retrieved using a single call to the API routine vpi_get_assertion_info() from an assertion handle. To retrieve the dynamic characteristics, the API extends the VPI call back routines to accommodate assertions and register call-backs on specific events,
such as start, stop etc.

Table 6.2.7.2.1-1 vpi_get() Arguments and Usage
vpiAssertAttemptCovered Extract the number of assertion attempts.
vpiAssertSuccessCovered Extract the number of true (non-vacuous)successes.
vpiAssertVacuousSuccessCovered Extract the number of vacuous successes
vpiAssertFailureCovered Extract the number of assertion failures

Ben Cohen SystemVerilog.us