Turn off vacuous success in SystemVerilog assertions

In reply to pRoSpEr:

It could be a NYI (Not Yet Implemented) issue.
Typically, NYI issues get resolved if

  1. The tool company decides to support the feature
  2. If customers (the $$ ones have more clout) request the feature.
    … and this is why some some vendor(s) (I leave the ID(s) nameless)
    are very weakly supporting 1800’2012, and weakly support 1800’95 for assertions.
    The major 3, and one more i know of, do support UVM.

You need to check with your vendor.
The $assertvacuousoff(0) Disables the pass action block for vacuous successes.
Question for you: Why do you even have pass action blocks. They are rarely used.
Ben Cohen SystemVerilog.us