Turn off constraints in pre-randomize method

SystemVerilog
1

Hi,

Can we turn off the constraint in pre-randomize method to avoid the randomization on some particular variables at some particular iteration.

Thanks in Advance

2

LRM 1800-2012 18.6.2

Every class contains pre_randomize() and post_randomize() methods, which are automatically called by randomize() before and after computing new random values.

Then you can not write constraint which disable the randomization on particular variable or on some iteration.

So you can write any condition which turn off the constraint(which is turn of the randomization on some variable).
like :
var_name.rand_mode(0);

3

In reply to rhariprasad:

In, SystemVerilog, turning off a constraint does not prevent randomization of a variable, it only turns off the constraint. And similarly, turning off the random mode of a variable does not remove the constraint. If you do not want to randomize a particular variable, you need to know if the constraint still hold, or need to be turned off as well.

You can also control randomization of a variable in a constraint

constraint hold {my_mode -> my_var == const'(my_var);}

If my_mode is true, my_var must hold its current state,

4

Hi Dave,

Thanks a lot for your quick response.
While solving the constraints itself we can maintain the current state means, we can switch off the constraints in pre-randomize method. So, this is what you concluded right? please correct me, if I am wrong.

Thanks in advance.