Turn off constraint

SystemVerilog
,
2

Hi

Yes , you can turn off constraints with

<object_name>.<constraint_name>.constraint_mode(0) ;

Example :

class Packet;

rand bit [3:0] sof;
rand bit [3:0] eop;
rand bit [7:0] data[];

constraint sof_c
{
sof < 8 ; sof > 2
}

constraint eop_c
{
eop < 8 ; eop > 2
}

endclass : Packet

Program main;

  Packet P = new();

 initial
   begin
    P.sof_c.constraint_mode(0) ; //turn off constraint sof_c

    P.randomize();

    P.sof_c.constraint_mode(1) ; //turn on constraint sof_c

    P.randomize();

    end
endprogram

Hope it is clear else refer SV LRM.

Thanks
Billa