Hi,
I have 8 instances of one RTL module which are generated using genvar in the Environment for which I want to bind all 8 instances of interface to the DUT. I tried the following piece of code for which I got an error saying:
Hierarchical name component lookup failed for ‘j’ ‘mod_tb.sub.par_top.top.chan.ctrl.dut’
CODE:
virtual bind_if bind_vif[7:0];
genvar j;
generate
for (j=0; j<8 ; j++) begin
bind `TOP.chan[j].ctrl.dut bind_if bind_vif[j](
.clk (Cclk ),
.reset (rst ),
.Valid (Valid ),
.ReadData (ReadData),
) ;
initial begin
uvm_config_db #(virtual interface bind_if)::set(null,"*", $sformatf("bind_vif_%0d",j),`TOP.chan[j].ctrl.dut.bind_vif[j]);
end
end
endgenerate
I am looking for a generic solution as above wherein in a loop I should be able to create 8 bind instances.
Thanks in advance.
In reply to n.madhushri:
Remove the [j] from bind_vif[j]. Just use `TOP.chan[j].ctrl.dut bind_if bind_vif.
Hi Dave,
If we have below situation: The design has multiple instances of a module in it. I am trying to connect output port of each such instance to a single sv interface array element thorugh bind.
It is giving error. Could you please help me to pinpoint my mistake
Design
module demod(output [9:0] demod_data);
// output [9:0] demod_data;
endmodule
module de_top();
genvar demod_inst;
generate
for (demod_inst = 0;demod_inst < 126;demod_inst = demod_inst+1)
begin : u_demod_gen
demod
u_demod (
.* //ports mapping done here
);
end
endgenerate
endmodule
tb:
interface test_if();
logic [9:0] demod_data[126];
endinterface
module test_top();
de_top u_de_top();
genvar demod_inst;
generate
for (demod_inst = 0;demod_inst < 126;demod_inst = demod_inst+1) begin
//bind dm:de_top.u_demod_gen.u_demod[demod_inst].demod_data test_if test_if1(.demod_data[demod_inst](demod_data));
bind demod:u_de_top.u_demod_gen.u_demod[demod_inst] test_if test_if1(.*);
end
endgenerate
endmodule
Thanks a million!
In reply to mahajana:
I believe your interface definition should be declared with a port.
interface test_if(
input logic [9:0] demod_data
);
endinterface
Hi Dave,
I tried that too. It was also giving the error
interface test_if(input logic [9:0] demod_data[126]);
endinterface
module test_top();
de_top u_de_top();
endmodule
module test_tp();
generate
genvar demod_inst;
for (demod_inst = 0;demod_inst < 126;demod_inst = demod_inst+1) //begin
bind demod:test_top.u_de_top.u_demod_gen.u_demod[demod_inst] test_if //test_if1(.*);
end
endgenerate
endmodule
In reply to mahajana:
Your generated instance path name is not quite correct. The named generate block gets iterated, not the module instance name. I find it helps looking at what $display %m prints before attempting the bind.
module demod(output wire [9:0] demod_data);
initial $display("demod %m");
endmodule
module de_top();
wire [9:0] demod_data_array[126];
for (genvar demod_inst = 0;demod_inst < 126;demod_inst++)
begin : u_demod_gen // [demod_inst]
demod u_demod (
.demod_data(demod_data_array[demod_inst])
);
end : u_demod_gen
endmodule
interface test_if(
input wire [9:0] demod_data
);
initial $display("bound %m");
endinterface
module test_top();
de_top u_de_top();
for (genvar demod_inst = 0;demod_inst < 126;demod_inst++) begin
bind demod:u_de_top.u_demod_gen[demod_inst].u_demod test_if tif(.*);
end
endmodule
Displays:
# demod test_top.u_de_top.u_demod_gen[0].u_demod
# bound test_top.u_de_top.u_demod_gen[0].u_demod.tif
# demod test_top.u_de_top.u_demod_gen[1].u_demod
# bound test_top.u_de_top.u_demod_gen[1].u_demod.tif
# demod test_top.u_de_top.u_demod_gen[2].u_demod
# bound test_top.u_de_top.u_demod_gen[2].u_demod.tif
# demod test_top.u_de_top.u_demod_gen[3].u_demod
# bound test_top.u_de_top.u_demod_gen[3].u_demod.tif
...
BTW, I have simplified your generate-for loop syntax. the genvar declaration can go right inside the for loop initialization, and the generate/endgenerate keywords are optional.
Hi Dave,
Thanks for the prompt responses.
I can’t modify the design module (de_top). I can’t add the wire in de_top. We have to develop a solution outside of it. I agree my path was incorrect earlier.
Is there a way to bind
interface test_if(
input wire [9:0] demod_data [126]
);
initial $display("bound %m");
endinterface
with the design
module demod(input [9:0] demod_data);
initial $display("demod %m");
// output [9:0] demod_data;
endmodule
module de_top();
generate
genvar demod_inst;
for (demod_inst = 0;demod_inst < 126;demod_inst = demod_inst+1)
begin : demod_gen
demod u_demod (.demod_data(demod_inst));
end
endgenerate
endmodule
In reply to mahajana:
There are a few things that still do not make any sense.
Before introducing the bind instance for the moment. Module demod has 1 10-bit port. Module de_top instatiates 126 instances of demod. You have never correctly shown or explained how each instance demod’s port gets connected in the de_top. I doubt you want the same 10 bits connected to each instance unless this is some kind of tri-state bus. Can you please show enough of an example that compiles without the bind?
The other thing is your interface test_if has 1 port that is a unpacked array of 126 elements with each element being 10 bits, for a total of 1260 bits. But you are trying bind 126 interfaces into each of the 126 demod instance that only have 10 bits. Or do you really only want one instance of test_if?
Thanks Dave! I found my mistake. Thanks to pointed questions :)
your interface test_if has 1 port that is a unpacked array of 126 elements with each element being 10 bits, for a total of 1260 bits. But you are trying bind 126 interfaces into each of the 126 demod instance that only have 10 bits. Or do you really only want one instance of test_if?- This helped