Tristate usage inside of a SV interface

SystemVerilog
1

Hi,

I’m looking for an example how to use a tristate bus inside of a
SV - Interface (Interface between TB and DUT).

Thanks,

Frodus

2

A tri-state bi-directional bus requires the use of Verilog wires. That is the only kind of signal that can resolve multiple drivers. Your TB can handle the bus signals the same as the DUT handles it - with continuous assignments.

interface my_if;
wire [31:0] bus;
logic [31:0] bus_reg = 'z;
assign bus = bus_reg;
modport DUT(inout bus);
modport TB(input bus, output bus_reg);
endinterface

You assign bus_reg to 'z when you want to read what the DUT is driving. You could also have a separate enable signal and have the statement

assign bus = enable ? bus_reg : 'z;

SystemVerilog gives you another option for your TB, called a clocking block, that simplifies things.

interface my_if;
wire [31:0] bus;
bit clk;
clocking cb @(posedge clk);
inout bus;
endclocking

modport DUT(inout bus);
modport TB(clocking cb);
endinterface

The clocking block creates two variables with the same name. When reading cb.bus, you get the variable that holds a sampled value of the bus signal. When writing cb.bus, you write to a variable that has an implicit continuous assignment to the bus signal. (with a delay synchronized to a clock event.
It