Tristate handling in interface

SystemVerilog
, ,
2

In reply to dipling:

Here while passing the interface to “dut_pad” module from the testbench, you are passing entire interface. While, the “dut_pad” only uses “my_ifc.pins” modport. When it passes the interface to “ifc_drv” module, the same “my_ifc.pins” is passed. While the “ifc_drv” expects “my_ifc.user” in the port list.

You need to make some changes in passing the interface to modules:

// In testbench
  dut_pad i_dut_pad (
    .ifc (ifc) // Pass full interface
  );

// In dut_pad
module dut_pad (
    my_ifc ifc
);
    ifc_drv drv (
      .ifc(ifc.user) // Pass user modport
    );

// In ifc_drv
module ifc_drv (
    my_ifc.user ifc
);

Somehow, you need to pass the correct port types for the “ifc_drv” module.