Triggering of assertion based on change in value of variable

SystemVerilog
1

1)is it legal to use vector variable as a sampling event in the property whih is shown in example 1 ?

logic[3:0]var;
bit a,b;
example 1 : property p1;
@(posedge var)
a|->b;
endproperty

  1. can any one provide the detailed explanation using systemverilog assertion events for the below example

property p2;
@(posedge a or posedge b)
a|->b;
endproperty

2

In reply to venky970:


1)is it legal to use vector variable as a sampling event in the property whih is shown in example 1 ?  ->  you should not use the vector on edge trigger event as it will always check for a transition of a least significant bit. 

logic[3:0]var;
bit a,b;
example 1 : property p1;
@(posedge var)
a|->b;
endproperty

2) can any one provide the detailed explanation using systemverilog assertion events for the below example this is illegal property as it becomes the multi-edge trigger.  whats your intent of this property? 

property p2;
@(posedge a or posedge b)
a|->b;
endproperty
3

In reply to kddholak:
whether below assertion is legal or illegal ,if legal whether it will trigger ?and how it will be evaluated ?

bit a,b,c;
property p1;
@(posedge a or posedge b)
(a||b) |-> c;
endproperty

assert property(p1);

4

In reply to venky970:

It’s legal. It’s nonsense. It executes by the same rules of any property. Do realize that if there is a posedge a, its sampled value will be 0. Same for b.

5

In reply to dave_59:
Thanks @dave_59
if posedge a is detected ,so can you please say why the value of a will be 0 instead of 1 though posedge a is detected ?

6

In reply to venky970:

Because assertions use sampled values of variables, which is the value they have at beginning of the time step before any activity. In order to have a posedge event on a bit, the value must transition from 0 to 1.