In reply to ben@SystemVerilog.us:
Hi Ben ,
With the delay of #1 and using covergroup frame @( cg_trig ) , auto[5] is covered
A few questions regarding the previous reply
(1)
this is not going to work in this case because the framelength is computed within the sequences, and it’s value needs to be copied to the module variable.
Won’t ( Detect_EOP.triggered ) return 1’b1 only when the sequence completes ?
i.e function trigger_cg would have been called ( framelength would be updated with cnt 5 ) before the sequence completes
(2) Regarding the vacuous pass reporting when $rose(SOP) is false .
Does the LRM discuss this part ? i.e Pass action block being executed when antecedent is false OR it depends upon tool ( 2 tools I tried don’t report the Vacuous pass )