In reply to ben@SystemVerilog.us:
Although cnt is 5 , bin auto[0] is covered i.e value of framelength of 0 is being hit instead of value 5 .
My guess is the SVG evaluation timing regions. Try the following and let me know what you get.
task trigger_cg (int length ) ; // input Arg. Same type as Actual Arg. i.e Local variable ' cnt '
framelength = length ;
#1; // Delay to bring the value of framelength stable in a new evaluation cyle
-> cg_trig ; // Trigger Covergroup Sampling
endtask