Tri1 in verilog

SystemVerilog
,
1

Hi,
can any one tell me the usage and property of a data type

 tri and tri1

in Verilog with example

Thanks

2

In reply to lalithjithan:

**wire** and **tri** are synonyms for the same kind of net. Originally **wire** was for single driven nets and **tri** was for nets with multiple drivers that needed tri-state strengths to resolve, but that was never enforced. SystemVerilog added **uwire** to represent a net allowing only one driver.

When a net has no drivers, or all driving Z, a
tri1 net will get pulled to the 1 state.

https://verificationacademy.com/forums/systemverilog/pullup-sv