The command sequence should follow the sequence ab → ob → b9 , the command sequence is exactly comming but assertion is failling ,THe sequence ab → 0b can happen minimum 1 and maximum 5 times .
I have used no clock
The way you wrote the property, your clocking event is @(posedge command).
Thus, when you say I have used no clock, you are incorrect, you are defining that clock to be the posedge command.
Assuming that your sequence is clocked with a clk, you most likely mean
Thanks Ben,
But still the sampling is not happening and assertion is failing still .
property command_sequence_check ;
@(posedge clk) disable iff(!rstn )
$rose(command) |-> sequ_A[*1:6] ##1 (i_mtx_byte == 8’hb9) ;
If your design and testbench follow the proper design rules and your requirements are met by this assertion and your directed tests are correct then you should not have an assertion error. My guess as to why you experiencing an assertion failure is because you either have not followed the proper rules or your test pattern is incorrect.
The rules I am talking about:
4. for the clock, use something like initial forever#10 clk=!clk;
5. for the design and testbench, use nonblocking assignments when updating variables
verilog always @(posedge clk) begin var <= a && b; end
6. consider using randomized variables after your directed tests. Something like:
verilog initial begin repeat(200) begin @(posedge clk); if (!randomize(a, b) with { a dist {1'b1:=1, 1'b0:=1}; b dist {1'b1:=1, 1'b0:=2}; }) `uvm_error("MYERR", "This is a randomize error"); end $finish; end
In reply to bijal thakkar:
A correction to a statement I made:
A $display of a variable used in the sequence_match_item uses the sampled variable and thus does not need the $sampled of that variable.
For example (a, $display(“a=%b”, a) ##1 b |-> c)