Top module is always visible for all components/sequences/object?

SystemVerilog
,
1

Hi, Dear,

I want to know if the top module is always visible for any elements inside the environment ?

module tb_top;
    intf1 intf();

    ......

endmodule

I want to know if I could directly access tb_top.intf no matter if I was in any object/component or even sequence ? Besides, I want to know how it could happen ? Does the Verilog/SV RLM specified the tb_top is always visible to entire environment ?

Thanks.

2

In reply to caowangyang:

Check out the 2017 LRM section 23.3.1. In particular if you want to unambiguously refer to a top-level module you should use $root.tb_top.intf.

You cannot (or should not be able to) refer to $root hierarchies from within a package.

3

In reply to sbellock:

thank for your reply, another question, may I know what’s the relationship between root and uvm_root ? Which one is the really top for the whole environment ? Or they actually could access mutually (one to another, or vice versa)?

4

In reply to caowangyang:

$root is the top of the module instance hierarchy that gets elaborated before simulation starts. It is declared using structural syntax. You can read more about it here.

uvm_root is a class variable inside the uvm_pkg. It represents the root of a tree structure of uvm_component instances created during simulation at time 0. It gets created by procedurally calling the run_test() task, which in turn calls the build_phase functions in each component. The UVM’s class based build_phase() is the procedural equivalent of SystemVerilog’s elaboration of modules.

One key difference is you cannot change the structural hierarchy of modules once simulation begins whereas you can use command line options, and file I/O, and randomizations to change the uvm_component hierarchy for each simulation run.

Since uvm_top is in a package, you can access it from anywhere. But from within a package, you are not allowed to access anything outside the package except by importing another package.