Token 'env' should be a valid type. Please declare it virtual if it is an Interface

SystemVerilog
1

Hello I am writing a verification code for LFSR(linear feedback shift register).I am using an online tool EDA playground (VCS 2014.12) . While writing a test class (code below). I am getting the following error

{token ‘env’ should be a valid type. Please declare it virtual if it
is an Interface.
“testbench.sv”, 34: token is ‘;’
env ev;}

Code for class test:
class test extends uvm_test;
`uvm_object_utils(test)

env ev;

function new(string name=“test”);
super.new(name);

endfunction

function void build_phase(uvm_phase phase);
ev = env::type_id::create(“ev”, this);
endfunction

task run_phase();

my_sequence seq;
phase.raise_objection(.obj(this));
seq.start(env.ag.seqr);
phase.end_objection(.obj(this));

endtask

endclass

Please give the solution for it on high priority

2

In reply to rajashekar.merugu:
I was able to regenerate your error only when I put env as class which I have not defined.
please check with your class name.
Also update your constructor with parent argument in test and check if env is registered with factory.

3

In reply to rajashekar.merugu:

where is your EDA playground link?
uvm_test is a component, and you should use

`uvm_component_utils

to register it with factory, not object.

Consequently, use this “new” prototype for a component:

function new( string name, uvm_component parent );
  super.new( name ,parent );
endfunction

Your run_phase should look like (inherited from uvm_component->uvm_test):

task run_phase(uvm_phase phase);
endtask

See if any of that helps first…

4

In reply to Ankur Jain4:

Thanks for your reply. I have used env as class name for environment class. It is declared as

env ev with env as class name and ev as its object instantiation. Can u please rectify my mistake?.Also please provide me with an exmaple for your statement “Also update your constructor with parent argument in test and check if env is registered with factory.”

5

In reply to bmorris:

eda link is Edit code - EDA Playground. You can find my entire code written der. Kindly let me know if any error or modification reqiuired

Cn u please let me know the ways to connect from driver to monitor

6

In reply to rajashekar.merugu:

class env extends uvm_env;
  `uvm_object_utils(env)
  
   
  monitor_after  ma;
  monitor_before mb;
  
  scoreboard sb;
  agent ag;
  
  
 
  function new(string name="env");
    super.new(name);
    
    /*ma=new("ma",this);
    mb=new("mb",this);
    sb=new("sb",this);*/
      

endfunction
  
  function void build_phase(uvm_phase phase);
    super.phase(uvm_phase); // this is wrong it has to be super.phase(phase);

Also, please update your factory registering macros from uvm_object_utils to uvm_component_utils for all the components.

7

In reply to rajashekar.merugu:

You have quite a few errors. I recommend going through the Mentor cookbook for each component type, or look at the examples on http://cluelogic.com/, etc.

Pay attention to which classes are components, and which classes are objects (sequence, sequence item, etc), and simply replicate those examples. Also, use “if” instead of “assert” for your randomize statements.

I would shrink the testbench size down dramatically until you understand the pieces, then build it back up. Understand a component vs object, what the constructors look like and why, which factory registrations to use. For example, just have your module top, and a test component class (with empty build_phase) etc. Get that compiling, then go from there.