In reply to gani:
$width i wanted to have min & max limits is it possible?.
It does not look this is allowed with the $width. 1800 states*"The pulse width has to be greater than or equal to limit in order to avoid a timing violation,
but no violation is reported for glitches smaller than the threshold. "*
My area of concentration is really assertions. Maybe with the a combination of the 1800 timing checks you can do that. An alternative is to use SVA. I updated the code, as shown below.
// With limits
property period_chk2;
realtime current_time, deltat;
('1,current_time = $time ) ##1
(1, deltat=$time- current_time) ##0 (deltat >= 9.99ns && deltat<= 10.01ns); //
endproperty
ap_time2: assert property(@(posedge clk) period_chk2);
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115