In reply to ben@SystemVerilog.us:
In reply to gani:
SVA is not intended for timing checks. The best solution is to use the SystemVerilog timing checks defined in 1800:31 Timing checks. These timing checks include:
$setup $hold $setuphold $recovery $removal $recrem
See the example that I provide in my SVA Handbook, 4th Edition.
http://SystemVerilog.us/setup_SVA_Handbook.pdf
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
`timescale 1ns/1ps;
module setup_time_check(input clk);
specify
//1)Expected to PASS ----------------->Ok no issue
$width(posedge clk,50);
$period(posedge clk,100);
//2)Expected to FAIl ------------------>I am not seeing any failure why???
$width(posedge clk,10);
$period(posedge clk,20);
//3)Expected to FAIl ------------------> Seen failure ok.
$width(posedge clk,60);
$period(posedge clk,200);
endspecify
endmodule
module top;
parameter PERIOD = 100;
reg clk=0,cke,ckel;
setup_time_check setup_time_check_i(.clk(clk),
.cke(cke)
);
initial forever #(PERIOD/2) clk = ~clk;
endmodule
I am not seeing any failure for 2nd comment ,please let me know?
Thanks,
NK