In reply to gani:
I am going to write checkers for DDR(model checks)
Please suggest me which is the best way to code these checkers .Means using timing timing checks($setup()) or using SVA assertions .
Please let me know the reason also why timing /SVA?
I seen couple of papers - I didn’t get conclusion
For setup time,hold time checks directly i can use $setup()-Is there any draw backs for this?
Which way is the best way & faster? timing checks or SVA checkers?
Thanks,
NK.
SVA is not intended for timing checks. The best solution is to use the SystemVerilog timing checks defined in 1800:31 Timing checks. These timing checks include:
$setup $hold $setuphold $recovery $removal $recrem
See the example that I provide in my SVA Handbook, 4th Edition.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115