In reply to ben@SystemVerilog.us:
No Ben.I wanted to check ,Is my checks are working as per expectation or not.
Like is it triggering or not in simulation?
If i want to check each timing check is working or not by creating a test bench for check and verify using random scenarios it’s time consuming process.Is there any way to check my checks are triggering as per expectation or not.
For eg in SVA we have coverage to check particular property is covered or not.
Thanks,
NK