I want to do some timing checks on signals generated by driver like setup and hold times and pulse widths.What should i do so that i can make transactions and do timing checks as well?
The best thing to do is use Verilog’s specify block timing checks in a module that is instantiated or bound into the testbench that connects to the signals generated by the driver.
Doing timing checks on your own requires many extra threads and is very inefficient, especially if your are indirectly referencing the clock through a virtual interface.
In reply to dave_59:
Agree fully with Dave’s suggestion. Incase you need a quick example, see: Verification Course Blog | VeriLog Courses | CVC - it has highlights on how Questa can help you debug such checker failures - almost instantaneously too!
Regards
Ajeetha, CVC
Thanks for the suggestion…But lets suppose i have to do that in monitor,i was thinking of using $setup,$hold etc for that.(if you know system verilog altrnative for these tasks,please do tell)
Im not sure if i can use a specify block inside monitor’s run task.Also specify block doesnt work on some compilers.
In reply to Umair:
Specify blocks along with $setup/$hold checks are only allowed within modules. These kinds of checks are really targeted towards gate-level designs and require accurate timing calculations usually annotated with SDF.