Timing Assertions

SystemVerilog
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9

In reply to Mrutunjay:


property check_b ;
 start && b && !a|-> ##[4:15] !b ;
endproperty 

property check_a_b ;
 start && a |-> b ;
endproperty 

property check_a_b ;
 start && a && $fell(b) |-> what will happen to a ? ;
endproperty